The interesting part of AI hardware at FMS 2026 was not another accelerator glamour shot. It was flash memory trying to sneak through the service entrance wearing a memory badge. That sounds like a small paperwork crime until you notice the names on the clipboard: SK hynix, Sandisk, UCIe, OCP, and a memory tier called G1.5. The old hierarchy was simple enough to explain with a bad diner analogy: DRAM is the counter, flash is the storeroom, and the GPU is the hungry line cook yelling for ingredients. High Bandwidth Flash asks a rude question. What if the storeroom moved close enough to the grill that the cook stopped waiting? ## The stack SK hynix drew in the margins According to Thomas Coughlin at Forbes, SK hynix and Sandisk used the 2026 FMS Conference to show High Bandwidth Flash work aimed at AI inference, not just ordinary storage throughput. The important bit was SK hynix’s tier language: G0.5 for 3D stacked DRAM, G1.5 for HBF, and G2.5 for CXL pooled memory, all described by Forbes as part of an effort to optimize xPU performance. That is not marketing confetti. It is a map of where the memory wall is cracking. SK hynix’s own newsroom said the company and Sandisk released the first open HBF standard through OCP, with up to 512GB capacity, up to 3TB/s bandwidth, and UCIe support. That combination is the tell. Flash is not just being asked to sit politely behind a storage controller anymore; it is being invited into the chip to chip conversation, which is where the expensive waiting happens. ## The buried spec is not capacity, it is locality Forbes reports that the first HBF specification spans capacities up to 512GB and bandwidths from 0.4TB/s to 3.0TB/s, using UCIe interconnect. The capacity number is the shiny jewel in the display case, but the interconnect is the getaway driver. UCIe matters because it frames HBF less like a distant SSD and more like a neighboring memory tier, close enough to change how inference systems are provisioned. Why should you care if you are building or buying AI infrastructure? Because inference cost often comes down to how long accelerators spend doing useful work versus waiting for bytes to show up with a tiny suitcase and a bad attitude. Forbes also reported that HBF demonstrated 2X GPU efficiency in AI inference compared with HBM. Treat that as a claim to watch through independent systems testing, but it explains why storage class memory ideas are creeping back into the AI stack with fresh shoes. ## Sandisk brings NAND to a DRAM knife fight The Elec reported that Sandisk announced on Aug. 6 that it would unveil AI focused NAND technologies at FMS 2026, including HBF. Forbes adds the more interesting teardown layer: Sandisk showcased BiCS8 and BiCS10 NAND technologies and positioned HBF as high capacity, high performance non volatile storage that could supplement or replace HBM in some roles. That is a bold assignment for flash, which historically got treated like the patient mule of the data center. SK hynix also said its 375 layer 4D NAND is 2.5 times more power efficient. Power efficiency is where the spreadsheet stops being boring and starts whispering in the CFO’s ear. If flash can provide a large nearby tier without turning the board into a panini press, then model serving designs get a new knob to turn besides buying more HBM. ## The GPU does not want a chaperone Chris Mellor at Blocks & Files captured the same architectural mood from a different aisle at FMS, reporting that DDN and Nvidia are testing a way for the GPU to request data itself instead of asking the CPU to fetch it first. Blocks & Files said the approach uses Nvidia’s SCADA architecture with DDN’s Infinia platform, with the goal of cutting a step and reducing idle time. Different plumbing, same lesson: the industry is attacking the dead air between accelerator demand and data arrival. Let’s talk about what they did not have to put in a keynote slide. The memory hierarchy is becoming less like a neat apartment building and more like a casino heist, with every tier trying to stand closer to the vault before the alarm goes off. HBM remains the premium table. HBF is the suspiciously well dressed accomplice offering capacity and bandwidth in a place flash did not normally get to stand. ## What to watch after FMS Forbes frames HBF as a possible supplement or replacement for HBM in AI inference, while SK hynix frames G1.5 between 3D stacked DRAM and CXL pooled memory. That middle position is the whole story. It suggests future inference servers may be judged less by peak compute alone and more by how intelligently they arrange data across HBM, HBF, DRAM, and pooled memory. For readers, the practical move is simple: watch the software stack, not just the package photos. If frameworks, runtimes, and system vendors can place the right inference data in the right tier, HBF becomes useful engineering. If they cannot, it becomes another excellent spec sheet hunting for a workload. And yes, watch thermals, because thermal throttling is where elegant memory diagrams go to betray you. ## Sources - High Bandwidth Flash Advances At The 2026 FMS ...

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