Pick up a Huawei Kirin 9030 and you are holding one of the most instructive semiconductor objects in recent memory: a chip that reaches a minimum metal pitch tighter than Intel's flagship node, built without the lithography tool that the industry long considered non-negotiable at this density. That is not a press release claim. That is what SemiAnalysis documented when their teardown engineering lab put the chip under the electron microscope. ## What Metal Pitch Actually Tells You Before the numbers, a quick orientation on the metric that matters here. Metal pitch is the center-to-center distance between adjacent wiring traces on the densest metal layer of a chip. Think of it like lane width on a highway: the narrower the lanes, the more traffic you can route through the same real estate. Tighter metal pitch means more transistors per square millimeter, which translates directly into more compute or more cache packed into the same die area. Node names like "5nm" or "7nm" are marketing labels with almost no geometric meaning at this point in the industry's history. Metal pitch is one of the few measurements that gives you a real, apples-to-apples number across fabs. With that grounding in place, here is the figure that SemiAnalysis surfaced in their Kirin 9030 teardown: SMIC N+3 ships with a minimum local metal pitch of 32.5 nm. Intel's Panther Lake CPUs, built on 18A, carry a minimum metal pitch of 36 nm, according to the same SemiAnalysis analysis. That is roughly 10% tighter for SMIC on this specific dimension, as reported by Windows Forum summarizing the teardown findings. SemiAnalysis frames the result honestly: the headline number is true but incomplete, describing it as a cherry-picked metric, because density on a single layer is only one axis of process quality. Efficiency, process control, and yield are the other axes, and they tell a more complicated story. ## The Multi-Patterning Engine Under the Hood Here is where the process engineering gets genuinely interesting. EUV lithography, the tool that TSMC, Samsung, and Intel all rely on for their most aggressive nodes, uses 13.5 nm wavelength light to print features, and it can define a dense metal layer in a single exposure. SMIC does not have EUV. The foundry works with DUV immersion scanners, which operate at 193 nm wavelength, as TechPowerUp confirms in their coverage of N+3's volume production milestone. That wavelength gap is not a rounding error: 193 nm is more than fourteen times longer than 13.5 nm, and wavelength is what fundamentally limits how small a feature you can resolve in a single shot. The engineering response to this constraint is multi-patterning. You split one dense layer into multiple sequential exposures, each printing a subset of the final pattern, then align and combine them. Dr. Robert Castellano's semiconductor newsletter explains the core challenge directly: more passes raise the odds of misalignment, which shows up as yield loss, meaning more dies fail or get down-binned. Tighter metal pitch amplifies that risk because crowded wiring shorts or breaks more easily when alignment is imperfect. What SMIC has demonstrated with N+3 is that design-technology co-optimization, or DTCO, combined with aggressive DUV multi-patterning, can close a surprising amount of the gap with EUV on the density dimension alone. The cost of that engineering feat is paid in process complexity, not in the number printed on the node label. ## What the Teardown Reveals About Process Quality The SemiAnalysis report is careful not to let the metal pitch headline run unchecked, and that precision is exactly what makes it worth studying. Their analysis finds that N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and DTCO, but pays for that in complexity, efficiency, and process control. N6 is not a leading-edge node by current standards; matching it via a more elaborate process route is real progress, and it should be recognized as such, while also being understood for what it is. For learners studying semiconductor process technology, the Kirin 9030 teardown is a valuable case study in why single-metric comparisons mislead. A chip that wins on minimum metal pitch can still trail on transistor density per area, power efficiency at a given frequency, or manufacturing yield. TechPowerUp notes that SMIC N+3 is a full generation ahead of the older N+2 node, which is the 7nm-class process used for Huawei's Ascend AI accelerators and infrastructure parts, so the progression is genuine. The lesson the teardown teaches is that process technology is a multidimensional problem, and any analyst, student, or engineer who reduces it to a single number is leaving most of the story on the table. ## Why This Matters for Anyone Learning Semiconductor Engineering The SMIC N+3 story is a practical demonstration of a principle that shows up constantly in engineering: constraints drive creativity. When the straightforward path is unavailable, engineers find another route, and sometimes that route reveals capabilities that the conventional approach had obscured. DUV multi-patterning was widely treated as a scaling dead end. The N+3 teardown shows that with sufficient investment in DTCO and process control, the ceiling is higher than many assumed. If you are studying chip design, process engineering, or semiconductor manufacturing, the SemiAnalysis teardown is worth reading in full. It models the analytical discipline that separates serious process evaluation from headline-chasing: measure the right things, report what you found, and be explicit about what the data does not prove. The AEI report on lithography and chip self-sufficiency provides useful policy context for how these manufacturing choices fit into the broader industry landscape. The next thing to watch is whether SMIC can improve yield at N+3 scale, because a tight metal pitch that ships at low volume and high cost is an engineering proof of concept. The same pitch shipping at high volume and competitive cost would be something else entirely. ## Sources - Is SMIC N+3's Metal Pitch Smaller than Intel 18A's?

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