Intel 18A: Panther Lake ships BSPDN, GAA, Foveros-S

A chip teardown is the part where voltage stops being a promise and starts leaving fingerprints. Intel has talked for years about a manufacturing comeback, but Panther Lake gives us something better than a roadmap slide: material evidence. SemiAnalysis opened up Intel’s latest consumer chip and found Intel 18A not as a slogan, but as transistors, wiring, carrier bonding, and packaging choices you can inspect layer by layer. For anyone who cares about silicon rather than stage lighting, that is the interesting part.

The actual silicon, not the slide

SemiAnalysis says Panther Lake debuts the first commercial implementation of backside power delivery, or BSPDN, introduces Intel’s first gate-all-around transistors, and showcases Foveros-S assembly. That is the full three act play: move power delivery behind the wafer, wrap the gate around the channel with RibbonFETs, and stitch the resulting tiles into a package that can actually ship. Gate-all-around is not just a prettier transistor cross section, it is a control scheme, like giving the gate a firm grip on the channel instead of asking it politely from one side of the room.

SemiAnalysis says its teardown traces Intel 18A from four-sheet RibbonFETs and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. That matters because these are the pieces that separate a real process from a diagram in a keynote. If the old frontside power network was a crowded service corridor full of both signal and power traffic, backside power is the secret freight elevator, moving current where it needs to go while clearing space above for signals.

@title What SemiAnalysis traced in 18A
@source Intel Panther Lake Teardown 18A BSPD GAAFET SemiAnalysis STEEL

  Foveros-S assembly
        │
  Bonded carrier
        │
  Backside wiring
        │
  Frontside wiring
        │
  Contacts
        │
  Gate stacks
        │
  RibbonFETs

@caption SemiAnalysis followed Intel 18A from transistor structure through wiring and package assembly.

The density number with teeth

TechPowerUp, summarizing the SemiAnalysis teardown, reports that Panther Lake’s 18A compute logic is similar in density to the TSMC N3E logic used in the 12-core Xe3 GPU tile. It also reports that SemiAnalysis put 18A about 18.6 percent denser than Intel 3 GPU logic using a representative-cell model. That is a meaningful gain because Intel changed transistor architecture and power delivery while still landing a commercial consumer chip, which is a little like rebuilding the plumbing and foundation while the apartment complex is taking tenants.

The caveat is the part worth taping to the lab bench. TechPowerUp says SemiAnalysis found that Intel 18A does not lead TSMC N3P, TSMC N2, or Samsung SF2 in peak density. SemiAnalysis also cautions that whole-die density depends on cell mix and placement, which is the polite semiconductor way of saying one number can lie beautifully if you let it stand alone.

The package tells the comeback story

Remio’s writeup of the SemiAnalysis report makes the broader point: Panther Lake shows Intel can manufacture gate-all-around transistors and backside power delivery at commercial scale, but it does not prove Intel is supplying every leading component itself. Remio notes that Panther Lake still combines Intel and TSMC manufacturing, with a high-end graphics tile using TSMC N3E and an I/O tile using the older TSMC N6 process. That hybrid reality is not a failure, it is the modern chiplet bargain: use the right fab for the right tile, then make the package behave like a single product.

This is where Foveros-S stops being packaging trivia and starts being system architecture. The compute tile can be Intel 18A, the graphics tile can come from TSMC N3E, and the I/O tile can ride a different process, but the customer experiences the package, not the procurement spreadsheet. Good packaging is the quiet getaway driver of advanced silicon: if it does its job, everyone talks about the cores and nobody asks how the tiles escaped the physics warehouse together.

What they did not mention in the keynote

SemiAnalysis frames Panther Lake as a shift from roadmap promises to shipped silicon, but it also says the material choices add capacitance, thermal resistance, and process complexity while improving gate control and reducing resistance. That is the tradeoff drawer where the real engineering lives. Backside power can help routing and resistance, but every extra integration step is another place for yield, heat, and reliability to demand tribute.

So the right read is neither victory lap nor doom chart. Panther Lake makes Intel 18A real in the only way that counts, inside a commercial chip that analysts can cut open and measure. The next thing to watch is not whether Intel can say 18A again with more confidence, it is whether future products show broader use of the node, better density across full dies, and packaging that keeps thermals from staging a tiny coup under your keyboard.