Topic desk
Recent stories and signals from the Hardware desk — editorial intelligence, not a curriculum outline.
Built with NVIDIA AI infrastructure and tied to Intelligence Center X, Siemens’ EDA agents show why tool-calling needs a physics cop.
The new AI Super Agent targets the unglamorous grind of PCB and advanced packaging: constraints, reuse, manufacturability, and multiphysics checks.
The Ireland expansion is a cleanroom level lesson in node demand, regional manufacturing, and why announcements are only the first wafer.
The EPYC Venice timing is more than a date. It is a map for understanding validation, firmware, packaging, and upgrade patience.
The spend is real, but capacity, timing, tooling, yields, and product mix decide when buyers feel relief.
The AI hardware race is shifting from lone chips to optical plumbing, interconnect topology, and rack-scale architecture.
Reuters says Meta plans production in September as it seeks double computing capacity, with custom silicon as a capacity lever.
The new Super Agent coordinates board, package, and multiphysics work, which is exactly where tidy chip plans meet physics with a crowbar.
A leak about Xe3P graphics suggests the humble desktop iGPU is graduating from spare tire to platform planning tool.
The mini PC lesson is delightfully physical: a bigger APU badge cannot outrun a narrow memory road.
AuraStack targets PCB and multi-chip packaging workflows, where electrical, thermal, and mechanical tradeoffs now decide AI system reality.
The rumored move from InFO-PoP to WMCM is really about feeding AI models and keeping heat from mugging the memory bus.
EPYC Venice arrives first, and its server specs are the cleanest preview of the architecture and platform clues to watch next.
MTIA is less a chip launch than a supply chain move, putting more of Meta's AI infrastructure under hardware it helps design.
Strix Halo, up to 128 GB RAM, and an internal battery turn the handheld PC into a very specific machine for people who need more than couch gaming.
The A9 Max is a neat reminder that integrated graphics need memory bandwidth as much as a fancy processor name.
Reuters says Meta plans to put Iris into production in September, and the real story is infrastructure control.
The rumored WMCM shift is a useful lesson in why phone AI can stall at the package, not only inside the chip.
The headline capex is real, but buyers should watch wafer starts, tool lead times, qualification, and packaging capacity before expecting relief.
The reported rack slip turns the spotlight from GPU specs to the stubborn physics of building a Vera Rubin Ultra midplane at scale.
A Nature paper argues diffusion-like models may want circuits built for probability, not another larger math furnace.
The interesting part is not the assistant demo, it is Amazon trying to own more of the silicon inside the device.
The useful lesson is not the argument, it is learning why a node label is a generation name, not a transistor tape measure.
The transistor story is real, but foundry customers buy capacity, trust, and ramp confidence.
The useful teardown is not the podium shot. It is the capex path from state strategy to private fabs.
China is funding a memory fab that trails the leaders by generations. The bet is not on winning benchmarks today , it's on eliminating a critical industrial dependency.
The MSI Claw 8 EX AI+ carries Intel's first dedicated handheld SoC, and early benchmarks put it ahead of AMD's best. Here is the architecture story behind that result.
Snap just answered 'will consumer AR hardware exist?' Now the harder question is what software justifies building on it.
AMD is reportedly in advanced talks to fabricate Zen 6 chips at Samsung, trading known yield risks for supply security , and the decision reveals how chipmakers think about foundry economics.
Two new systems launched June 15, 2026 reveal that precision deposition and selective etch, not transistor design, are now the active constraints on vertical chip scaling.
Intel disclosed a real milestone at the 2026 VLSI Symposium, and the number that matters most is not the one getting the headlines.
A standard silicon carbide transistor, reconfigured at 10 millikelvin, fires brain-like spikes inside a quantum computer's freezer. Here is the physics behind why that matters.
SemiAnalysis reverse-engineered the Kirin 9030 and found a 32.5 nm minimum metal pitch. Here is what that number teaches you about process technology.
With commercial production underway at Micron and Kaynes, India's semiconductor policy is making a deliberate shift toward the harder problem: owning the supply chain that feeds the fabs.
Alphabet's 2028 chip order is a quiet but consequential vote for a second advanced-node supplier, and Nvidia may be watching closely.
When a dominant architecture tightens its grip, open-source alternatives stop looking like experiments and start looking like infrastructure.